Present complementary metal oxide semiconductor (CMOS) synchronous dynamic random access memory (SDRAM) circuits are frequently used for main memory in a variety of applications including desk top and portable computer systems. Advances in system technology continually reduce feature sizes and gate dielectric thickness. Internal operating voltages must be closely regulated for these reduced feature sizes and gate dielectric thickness in order to maintain reliability. Moreover, this regulation must be effective over a wide range of external voltage and temperature.
Regulation of internal high voltage supplies, such as Vpp, for SDRAM circuits is particularly critical due to the relatively high electric field across the gate dielectric of memory cells during a memory operation. Large variations in high voltage supply Vpp may degrade memory cell transistor performance characteristics over time and even lead to dielectric rupture and field failure of SDRAM memory cells. Previous regulation attempts were based on detecting an increase of high voltage Vpp by an integral number of transistor threshold voltages above supply voltage Vdd. When this excess value of Vpp was detected, a Vpp supply generator circuit would be temporarily disabled until high voltage supply Vpp attained a desired value. This method, however, fails to closely regulate the value of high voltage Vpp due to a wide variation of transistor threshold variation with temperature and process parameter variations.